//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
//Date        : Wed Nov 13 00:02:10 2019
//Host        : DESKTOP-EVCEGS1 running 64-bit major release  (build 9200)
//Command     : generate_target EDA1_TOP_v3.bd
//Design      : EDA1_TOP_v3
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CORE_GENERATION_INFO = "EDA1_TOP_v3,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=EDA1_TOP_v3,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=20,numReposBlks=20,numNonXlnxBlks=5,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=9,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "EDA1_TOP_v3.hwdef" *) 
module EDA1_TOP_v3
   (A0,
    A1,
    A2,
    APM,
    B0,
    B1,
    B2,
    BPM,
    CLK100M,
    DA,
    DB,
    DC,
    DD,
    DE,
    DF,
    DG,
    EN0,
    EN1,
    EN2,
    EN3,
    PMA,
    PMB,
    PMY);
  input A0;
  input A1;
  input A2;
  input APM;
  input B0;
  input B1;
  input B2;
  input BPM;
  input CLK100M;
  output DA;
  output DB;
  output DC;
  output DD;
  output DE;
  output DF;
  output DG;
  output EN0;
  output EN1;
  output EN2;
  output EN3;
  output PMA;
  output PMB;
  output PMY;

  wire A0_1;
  wire A1_1;
  wire A2_1;
  wire APM_1;
  wire Add_1bit_0_CO;
  wire Add_1bit_0_Y;
  wire Add_1bit_1_CO;
  wire Add_1bit_1_Y;
  wire Add_1bit_2_CO;
  wire Add_1bit_2_Y;
  wire Add_1bit_3_CO;
  wire Add_1bit_3_Y;
  wire Add_1bit_4_CO;
  wire Add_1bit_4_Y;
  wire Add_4bit_v3_0_Y0;
  wire Add_4bit_v3_0_Y1;
  wire Add_4bit_v3_0_Y2;
  wire Add_4bit_v3_0_Y3;
  wire Add_4bit_v3_0_Y4;
  wire B0_1;
  wire B1_1;
  wire B2_1;
  wire BPM_1;
  wire Complement_4bit_v3_0_Y0;
  wire Complement_4bit_v3_0_Y1;
  wire Complement_4bit_v3_0_Y2;
  wire Complement_4bit_v3_0_Y3;
  wire Complement_4bit_v3_1_Y0;
  wire Complement_4bit_v3_1_Y1;
  wire Complement_4bit_v3_1_Y2;
  wire Complement_4bit_v3_1_Y3;
  wire Complement_5bit_0_Y0;
  wire Complement_5bit_0_Y1;
  wire Complement_5bit_0_Y2;
  wire Complement_5bit_0_Y3;
  wire Complement_5bit_0_Y4;
  wire [0:0]xlconstant_0_dout;
  wire [0:0]xlconstant_1_dout;
  wire xup_2_to_1_mux_0_y;
  wire xup_2_to_1_mux_1_y;
  wire xup_2_to_1_mux_2_y;
  wire xup_2_to_1_mux_3_y;

  assign A0_1 = A0;
  assign A1_1 = A1;
  assign A2_1 = A2;
  assign APM_1 = APM;
  assign B0_1 = B0;
  assign B1_1 = B1;
  assign B2_1 = B2;
  assign BPM_1 = BPM;
  assign PMA = APM_1;
  assign PMB = BPM_1;
  assign PMY = Complement_5bit_0_Y4;
  EDA1_TOP_v3_Add_1bit_0_3 Add_1bit_0
       (.A(Complement_5bit_0_Y0),
        .B(xlconstant_0_dout),
        .CI(xlconstant_0_dout),
        .CO(Add_1bit_0_CO),
        .Y(Add_1bit_0_Y));
  EDA1_TOP_v3_Add_1bit_1_2 Add_1bit_1
       (.A(Complement_5bit_0_Y1),
        .B(xlconstant_1_dout),
        .CI(Add_1bit_0_CO),
        .CO(Add_1bit_1_CO),
        .Y(Add_1bit_1_Y));
  EDA1_TOP_v3_Add_1bit_2_2 Add_1bit_2
       (.A(Complement_5bit_0_Y2),
        .B(xlconstant_1_dout),
        .CI(Add_1bit_1_CO),
        .CO(Add_1bit_2_CO),
        .Y(Add_1bit_2_Y));
  EDA1_TOP_v3_Add_1bit_3_3 Add_1bit_3
       (.A(Complement_5bit_0_Y3),
        .B(xlconstant_0_dout),
        .CI(Add_1bit_2_CO),
        .CO(Add_1bit_3_CO),
        .Y(Add_1bit_3_Y));
  EDA1_TOP_v3_Add_1bit_4_1 Add_1bit_4
       (.A(xlconstant_0_dout),
        .B(xlconstant_1_dout),
        .CI(Add_1bit_3_CO),
        .CO(Add_1bit_4_CO),
        .Y(Add_1bit_4_Y));
  EDA1_TOP_v3_Add_4bit_v3_0_0 Add_4bit_v3_0
       (.A0(Complement_4bit_v3_0_Y0),
        .A1(Complement_4bit_v3_0_Y1),
        .A2(Complement_4bit_v3_0_Y2),
        .APM(Complement_4bit_v3_0_Y3),
        .B0(Complement_4bit_v3_1_Y0),
        .B1(Complement_4bit_v3_1_Y1),
        .B2(Complement_4bit_v3_1_Y2),
        .BPM(Complement_4bit_v3_1_Y3),
        .Y0(Add_4bit_v3_0_Y0),
        .Y1(Add_4bit_v3_0_Y1),
        .Y2(Add_4bit_v3_0_Y2),
        .Y3(Add_4bit_v3_0_Y3),
        .Y4(Add_4bit_v3_0_Y4));
  EDA1_TOP_v3_Complement_4bit_v3_0_3 Complement_4bit_v3_0
       (.A0(A0_1),
        .A1(A1_1),
        .A2(A2_1),
        .PM(APM_1),
        .Y0(Complement_4bit_v3_0_Y0),
        .Y1(Complement_4bit_v3_0_Y1),
        .Y2(Complement_4bit_v3_0_Y2),
        .Y3(Complement_4bit_v3_0_Y3));
  EDA1_TOP_v3_Complement_4bit_v3_1_1 Complement_4bit_v3_1
       (.A0(B0_1),
        .A1(B1_1),
        .A2(B2_1),
        .PM(BPM_1),
        .Y0(Complement_4bit_v3_1_Y0),
        .Y1(Complement_4bit_v3_1_Y1),
        .Y2(Complement_4bit_v3_1_Y2),
        .Y3(Complement_4bit_v3_1_Y3));
  EDA1_TOP_v3_Complement_5bit_0_1 Complement_5bit_0
       (.A0(Add_4bit_v3_0_Y0),
        .A1(Add_4bit_v3_0_Y1),
        .A2(Add_4bit_v3_0_Y2),
        .A3(Add_4bit_v3_0_Y3),
        .PM(Add_4bit_v3_0_Y4),
        .Y0(Complement_5bit_0_Y0),
        .Y1(Complement_5bit_0_Y1),
        .Y2(Complement_5bit_0_Y2),
        .Y3(Complement_5bit_0_Y3),
        .Y4(Complement_5bit_0_Y4));
  EDA1_TOP_v3_Digits_dynamic_displ_0_0 Digits_dynamic_displ_0
       (.AN0({1'b0,1'b0,1'b0,1'b0}),
        .AN1({1'b0,1'b0,1'b0,1'b0}),
        .AN2({1'b0,1'b0,1'b0,1'b0}),
        .AN3({1'b0,1'b0,1'b0,1'b0}),
        .clk100(1'b0));
  EDA1_TOP_v3_xlconcat_0_4 xlconcat_0
       (.In0(A0_1),
        .In1(A1_1),
        .In2(A2_1),
        .In3(xlconstant_0_dout));
  EDA1_TOP_v3_xlconcat_1_2 xlconcat_1
       (.In0(B0_1),
        .In1(B1_1),
        .In2(B2_1),
        .In3(xlconstant_0_dout));
  EDA1_TOP_v3_xlconcat_2_2 xlconcat_2
       (.In0(Add_1bit_4_CO),
        .In1(xlconstant_0_dout),
        .In2(xlconstant_0_dout),
        .In3(xlconstant_0_dout));
  EDA1_TOP_v3_xlconcat_3_1 xlconcat_3
       (.In0(xup_2_to_1_mux_3_y),
        .In1(xup_2_to_1_mux_2_y),
        .In2(xup_2_to_1_mux_1_y),
        .In3(xup_2_to_1_mux_0_y));
  EDA1_TOP_v3_xlconstant_0_3 xlconstant_0
       (.dout(xlconstant_0_dout));
  EDA1_TOP_v3_xlconstant_1_1 xlconstant_1
       (.dout(xlconstant_1_dout));
  EDA1_TOP_v3_xup_2_to_1_mux_0_3 xup_2_to_1_mux_0
       (.a(Add_1bit_3_Y),
        .b(Complement_5bit_0_Y3),
        .select(Add_1bit_4_Y),
        .y(xup_2_to_1_mux_0_y));
  EDA1_TOP_v3_xup_2_to_1_mux_1_2 xup_2_to_1_mux_1
       (.a(Add_1bit_2_Y),
        .b(Complement_5bit_0_Y2),
        .select(Add_1bit_4_Y),
        .y(xup_2_to_1_mux_1_y));
  EDA1_TOP_v3_xup_2_to_1_mux_2_2 xup_2_to_1_mux_2
       (.a(Add_1bit_1_Y),
        .b(Complement_5bit_0_Y1),
        .select(Add_1bit_4_Y),
        .y(xup_2_to_1_mux_2_y));
  EDA1_TOP_v3_xup_2_to_1_mux_3_1 xup_2_to_1_mux_3
       (.a(Add_1bit_0_Y),
        .b(Complement_5bit_0_Y0),
        .select(Add_1bit_4_Y),
        .y(xup_2_to_1_mux_3_y));
endmodule
